Conventional complementary metal-oxide-semiconductor (CMOS) devices offer higher on-current for n-type field effect transistors (NFETs) than for p-type field effect transistors (PFETs) having similar physical dimensions. This is, in general, due to higher electron mobility than hole mobility in most semiconductor materials. In the case of a silicon substrate having a (100) surface, the ratio of electron mobility to hole mobility is about 2. Correspondingly, semiconductor circuits have been designed to factor in the differences in the on-current per unit width of NFETs and PFETs.
Static random access memory (SRAM) is a memory device employing six transistors. SRAM cell design typically begins by picking the smallest PFET supported by a given technology for two pull-up PFETs, followed by scaling of NFET pass gate transistors and pull-down NFET transistors for optimal beta ratio, cell stability, and access time.
Referring to FIGS. 1A-1C, an exemplary prior art SRAM cell structure comprises a first planar pull-up PFET 116, a second planar pull-up PFET 116′, two planar pull-down NFETs (114, 114′), and two planar pass gate NFETs (112, 112′). FIG. 1A is a top-down view of a layout for the exemplary SRAM cell up to the contact-to-active area (CA) level not showing a middle-of-line (MOL) dielectric 170. FIG. 1B is a vertical cross-sectional view of the exemplary SRAM cell along the plane B-B′ showing the MOL dielectric 170. FIG. 1C is a vertical cross-sectional view of the exemplary SRAM cell along the plane C-C′ showing the MOL dielectric 170. Each of the transistors (112, 112′, 114, 114′, 116, 116′) comprises a portion of the semiconductor substrate 110, a portion of a gate dielectric 130, a portion of gate electrodes 132, portions of gate spacers 134, portions of active area (AA) silicides 160, and a portion of gate top silicides 164.
The gate dielectric 130 may comprise a conventional semiconductor oxide based dielectric material such as silicon oxide or silicon nitride. Alternately, the gate dielectric 130 may comprise a high dielectric constant (high-k) material having a dielectric constant greater than 4.0, and typically greater than 7.0. The gate electrodes 132 may comprise a doped polycrystalline semiconductor material such as doped polysilicon. Alternately, the gate electrodes 132 may comprise a metal gate material known in the art.
A shallow trench isolation structure 120 physically separates the transistors (112, 112′, 114, 114′, 116, 116′) and provides electrical isolation among the transistors (112, 112′, 114, 114′, 116, 116′). CA contact vias 176 and CA bars 178 are employed to provide electrical wiring among the transistors (112, 112′, 114, 114′, 116, 116′). One of the CA bars 178, which contacts one of the active area (AA) silicides 160 of the first planar pull-up PFET 116 as well as the gate top silicides 164 of the second planar pull-up PFET 116′ as shown in FIG. 1B, provides electrical connection between the drain of the first planar pull-up PFET 116 and the gate of the second planar pull-up PFET 116′. Likewise, another CA bar 178 provides electrical connection between the drain of the second planar pull-up PFET 116′ and the gate of the first planar pull-up PFET 116.
Each of the active areas for the planar pass gate NFETs (112, 112′) has a first width W1, and each of the active areas for the planar pull-down NFETs (114, 114′) has a second width W2. A beta ratio, which is the ratio of an on-current of each of the planar pull-down NFETs (114, 114′) to an on-current of each of the planar pass gate NFETs (112, 112′), is substantially the same as the ratio of the second width W2 to the first width W1. Typically, the planar pass gate NFETs (112, 112′) and the planar pull-down NFETs (114, 114′) have the same threshold voltage. It has been shown that the beta ratio needs to be close to 2.0 for optimal cell stability of an SRAM cell. Thus, the ratio of the second width W2 to the first width W1 is close to 2.0 in the exemplary prior art SRAM cell.
Referring to FIG. 2, a circuit schematic 118 for the exemplary prior art SRAM cell shows a first pair of a first pass gate n-type field effect transistor (NFET) 102 and a first pull-down n-type field effect transistor (NFET) 104. A first source/drain of the first pass gate NFET 102 and a first drain of the first pull down NFET 104 are adjoined to form an electrical connection at a first internal node 111. In the physical structure, this electrical connection is achieved by a first active area that contains both the first source/drain of the first pass gate NFET 102 and the first drain of the first pull-down NFET 104. Similarly, a second source/drain of the second pass gate NFET 102′ and a second drain of a second pull-down NFET 104′ are adjoined to form another electrical connection at a second internal node 111′. In the physical structure, this electrical connection is achieved by a second active area that contains both the second source/drain of the second pass gate NFET 102′ and the second drain of the second pull-down NFET 104′. The circuit schematic 118 further comprises a first pull-up p-type field effect transistor (PFET) 106 containing a third drain, which is physically a third active area, and a second pull-up PFET 106′ containing a fourth drain, which is physically a fourth active area. Each of the source/drain nodes of the pass gate transistors (102, 102′) may function as a source or a drain depending on the operation of the SRAM circuit. The sources of the first and second pull-up PFETs (106, 106′) are connected to a circuit supply voltage VCS through a power supply wiring 119. The sources of the first and second pull-down NFETs (104, 104′) are connected to ground.
The third active area is electrically connected to the first active area via a collection of a first contact via, a first M1 wire, and a first CA bar. This connection is represented in the circuit schematic 118 by the first internal node 111. Similarly, the fourth active area is electrically connected to the second active area via a collection of a second contact via, a second M1 wire, and a second CA bar. This connection is represented in the circuit schematic 118 by the second internal node 111′. The gates of the second pull-up PFET 106′ and the second pull-down NFET 104′ are adjoined to the third drain of the first pull-up PFET 106 via the first CA bar. This connection is represented in the circuit schematic 118 by a third internal node 113A and a fourth internal node 113B. The gates of the first pull-up PFET 106 and the first pull-down NFET 104 are adjoined to the fourth drain of the second pull-up PFET 106′ via the first CA bar. This connection is represented in the circuit schematic 118 by a fifth internal node 113A′ and a sixth internal node 113B′. The internal nodes (111, 111′, 113A, 113B, 113A′, 113B′) are connected by CA contact vias 176 and CA bars 178 as well as M1 wires (not shown). Typically, the first internal node 111 is connected to the third internal node 113A at M1 level. Likewise, the second internal node 111′ is connected to the fifth internal node 113A′ at M1 level. The connection between the third internal node 113A and the fourth internal node 113B is effected by one of the CA bars 178. Likewise, the connection between the fifth internal node 113A′ and the sixth internal node 113B′ is effected by another of the CA bars 178. The M1 level wiring is also used for routing of the word lines (117, 117′). The M2 level wiring is used for routing of the bit lines (115, 115′). M3 and M4 levels (not shown) are used for a power supply voltage network and a ground network.
In general, three functionality aspects that are critical to functional yields of an SRAM cell include writability, readability, and stability. Writability refers to the ease, noise immunity, and reproducibility of write operations on the SRAM cell. Readability refers to the ease, noise immunity, and reproducibility of read operations of the SRAM cell. Stability refers to noise immunity of the data stored in the SRAM cell. Typically, enhancement of one of the three functional characteristics accompanies degradation of at least one of the other two functional characteristics.
In view of the above, there exists a need for an SRAM cell structure providing enhancement of at least one of writability, readability, and stability of an SRAM cell without degrading any of the other functional characteristics. Particularly, there exists a need for an SRAM cell structure providing simultaneous enhancement of all three functional characteristics, i.e., writability, readability, and stability of the SRAM cell. Further, there exist a need for an improved SRAM circuit achieving such functional enhancements, and methods of manufacturing the SRAM cell structure providing such functional advantages.